1. Field of the Invention
The present invention generally relates to solid state image sensors and, more particularly, to a solid state image sensor or charge coupled device image sensor of an FIT (frame-interline transfer) type.
2. Description of the Prior Art
An example of a vertical FIT type solid state image sensor according to the prior art is shown in FIGS. 1 through 3.
Throughout FIGS. 1 to 3, reference numeral 1 designates an image pickup or imaging section, 2 a storage section, and 3 an output section, that is, a horizontal shift register section of a CCD (charge coupled device) structure, respectively. The imaging section 1 is formed of a number of light receiving elements or photoelectric-converting elements 4 arranged in a matrix fashion and a vertical shift register 5 of a CCD structure for transferring signal charges of the light receiving elements 4 in the vertical direction and located on one side of each of vertically arrayed light receiving elements 4. The storage section 2 is located under the imaging section 1 in the vertical direction and adapted to temporarily store the signal charges generated in the imaging section 1. The storage section 2 is comprised of a plurality of vertical shift registers 6 of CCD structure which correspond to the vertical shift registers 5 of the imaging section 1 in a one-to-one relation (1:1).
Each of the vertical shift registers 5 and 6 in the imaging section 1 and the storage section 2 employs a 4-phase driving system and is controlled, for example, by 4-phase drive pulses .phi.IM.sub.1, .phi.IM.sub.2, .phi.IM.sub.3, .phi.IM.sub.4 and .phi.ST.sub.1, .phi.ST.sub.2, .phi.ST.sub.3, .phi.ST.sub.4. As shown in FIG. 2, four transfer sections VR (VR.sub.1, VR.sub.2, VR.sub.3, VR.sub.4), each having a transfer electrode are made 1 bit. In the vertical shift register 5 of the imaging section 1, two transfer sections VR.sub.1, VR.sub.2 and two transfer sections VR.sub.3, VR.sub.4 correspond to the light receiving elements 4, respectively. Between each of the light receiving elements 4 and the vertical shift register 5, there is provided a read-out gate section (ROG) 7. In FIG. 2, hatched areas 8 represent channel stop regions. The horizontal shift register 3 of the output section employs, for example, a 2-phase drive system in which it is controlled by 2-phase drive pulses .phi.H.sub.1 and .phi.H.sub.2. In the horizontal shift register 3, a first storage section st.sub.1, a first transfer section tr.sub.1, a second storage section st.sub.2 and a second transfer section tr.sub.2 form one bit and this 1 bit corresponds to one vertical shift register 6 of the storage section 2.
FIG. 3 is a cross-sectional view taken along the line A--A in FIG. 2. In the horizontal shift register 3, on the surface of a P-type silicon substrate 11 formed is an N-type buried channel layer 12, and transfer electrodes 14 are formed through an insulating film 13 on the buried channel layer 12, thus the respective transfer sections, that is, the first storage section st.sub.1, the first transfer section tr.sub.1, the second storage section st.sub.2 and the second transfer section tr.sub.2 being formed. The transfer electrodes 14 of first storage section st.sub.1 and first transfer section tr.sub.1 are connected commonly to a bus line to which the drive pulse .phi.H.sub.1 is applied, while the transfer electrodes 14 of second storage section st.sub.2 and second transfer section tr.sub.2 are commonly connected to a bus line to which the drive pulse .phi.H.sub.2 is applied.
In the vertical type FIT solid state imaging element 15, during the vertical blanking period, the signal charges of the light receiving elements 4 are read out to the vertical shift registers 5 through the read-out gate sections 7, transferred through the vertical shift registers 5 and then temporarily stored in the storage section 2. At every horizontal blanking period, the signal charge at every horizontal line is transferred from the storage section 2 to the horizontal shift register section 3. The signal charge of one horizontal line transferred to the horizontal shift register section 3 is transferred in the horizontal direction in the horizontal shift register section 3 and then outputted.
FIG. 4 shows an example of a horizontal type FIT solid state imaging element 16 (described in Japanese Laid-Open Patent Publication No. 61-125077). This horizontal type FIT imaging element 16 is formed such that the storage section 2 is located at one side of imaging section 1 in the horizontal direction and the horizontal shift register section 3 of the output section is located at the lower side of the storage section 2 in the vertical direction. In the imaging section 1, a number of light receiving elements 4 are arrayed in a matrix configuration and at one side of each row of horizontally-arrayed light receiving elements 4, there is located a horizontal shift register 17 which corresponds to the vertical shift register 5 of the former example. The horizontal shift register 17 can employ a 3-phase drive system which is controlled, for example, by 3-phase drive pulses .phi.IM.sub.1, .phi.IM.sub.2 and .phi.IM.sub.3 shown in FIG. 4. In this case, as shown in FIG. 5, three transfer sections VR (VR.sub.1, VR.sub.2, VR.sub.3), each having a transfer electrode, are made as 1 bit and this 1 bit corresponds to each light receiving element 4. The signal charge from each of the light receiving elements 4 is transferred to the horizontal shift register 17 through the read-out gate section (ROG) 7, transferred in the horizontal direction and then stored in the storage section 2 temporarily.
The storage section 2 comprises a plurality of horizontal shift registers 18 which correspond to the horizontal shift registers 17 in the imaging section 1 at one-to-one relation (1:1). The adjacent horizontal shift registers 18 are coupled through a gate section (transfer channels SR.sub.5 controlled by a gate electrode) 19 for transferring the signal charge in the vertical direction as shown in FIG. 5. Each of the horizontal shift registers 18 employs, for example, a 4-phase drive system which is controlled by 4-phase drive pulses .phi.ST.sub.1, .phi.ST.sub.2, .phi.ST.sub.3, .phi.ST.sub.4 and in which four transfer sections SR (SR.sub.1, SR.sub.2, SR.sub.3, SR.sub.4) are made as 1 bit and two transfer sections SR.sub.2, SR.sub.1 in the upper horizontal shift registers 18 are coupled through the gate section 19 to two transfer sections SR.sub.4, SR.sub.3 in the adjacent lower horizontal shift register 18. Since the respective transfer sections SR.sub.1, SR.sub.2, SR.sub.3, SR.sub.4 of each of the horizontal shift registers 18 are respectively formed in correspondence to one another in the vertical direction, the gate section 19 is formed in a slant direction in order to couple the transfer sections which are displaced each other by a half bit. In the storage section 2, the vertical transfer of the signal charge to the output side thereof (to the horizontal shift register section 3) is carried out in a so-called zigzag fashion in which the charges in the transfer sections SR.sub.2, SR.sub.1 are transferred to the transfer sections SR.sub.4, SR.sub.3 by a half bit in the horizontal
direction and then transferred to the transfer sections SR.sub.2, SR.sub.1 of the lower stage of the horizontal shift register 18.
The horizontal shift register section 3 of the output section is formed of two horizontal shift registers, namely, a first horizontal shift register 20 and a second horizontal shift register 21. The first and second horizontal shift registers 20 and 21 are coupled through a gate section (i.e., a transfer channel controlled by a gate electrode) 22. Each of the first and second horizontal shift registers 20 and 21 employ, for example, 2-phase drive system which is controlled by 2-phase drive pulses .phi.H.sub.1 and .phi.H.sub.2. In this case, a first storage section st.sub.1, a first transfer section tr.sub.1, a second storage section st.sub.2 and a second transfer section tr.sub.2 form one bit which corresponds to one bit of the horizontal shift register 18 of the storage section 2. The second storage and transfer sections st.sub.2 and tr.sub.2 of the first horizontal shift register 20 are coupled to the
first storage and transfer sections st.sub.1 and tr.sub.1 of the second horizontal shift register 21 through the gate section 22. In that case, the corresponding storage and transfer sections of the first and second horizontal shift registers 20 and 21 are formed to correspond to one another in the vertical direction so that the gate section 2 is formed to be inclined.
In the horizontal shift register section 3, there is line-transferred the signal charge of the horizontal line from the storage section 2. That is, signal charges of the light receiving elements 4 on, for example, an odd horizontal line are transferred to the first horizontal shift register 20, while the signal charges of the light receiving elements 4 on an even horizontal line are transferred to the second horizontal shift register 21. Then, these signal charges are transferred at the same time in the horizontal direction so that the signal charges of two horizontal lines are outputted simultaneously.
In the horizontal type FIT solid state imaging elements 16, since the horizontal pitch (i.e., one bit distance) of the horizontal shift registers 18 in the storage section 2 does not depends on the light receiving system, the horizontal pitch 16 can be designed freely. Thus, the horizontal pitch of the horizontal shift register section 3 at the output section can be designed with a room. Therefore, even when the imaging section 1 is made high in image density, the horizontal shift registers 20 and 21 of the output section can be formed. Thus, it is possible to make the FIT type solid state imaging element with high image density.
In the vertical type FIT solid state imaging element 15, as shown in FIG, 6, a width W.sub.1 of one pixel (one cell) a of the imaging section 1 corresponds to a transfer channel width W.sub.2 of the vertical shift register 6 in the storage section 2 and then a horizontal pitch (i.e., length of one bit) X.sub.1 of the horizontal shift register section 3 at the output section is determined correspondingly. Therefore, if the number of pixels, particularly the number of pixels in the horizontal direction is increased, then the length X.sub.1 of one bit in the horizontal shift register section 3 is reduced, which requires a fine pattern technique. Further, the transfer channel width W.sub.2 of the vertical shift register 6 is reduced so that various problems such as the deterioration of transfer efficiency or the like occur.
In the horizontal type FIT solid state imaging element 16, if as shown in FIG. 7 the area of one pixel (one cell) a in the imaging section 1 is selected to be the same as that of FIG. 6, then a horizontal pitch (i.e., one bit length) P of the horizontal shift registers 18 in the storage section 2 can be increased so that a horizontal pitch (one bit length) X.sub.2 of the horizontal shift register section 3 at the output section can also be increased. Thus, the solid state imaging element 16 can be made high in pixel density. However, when the horizontal pitch P of the horizontal shift registers 18 in the storage section 2 is selected to be long, then the chip size of the whole solid state imaging element becomes large and the ratio between the width W and the length L of the horizontal shift register 18 is reduced so that the transfer efficiency of the storage section 2 in the frame transfer (i.e., when the signal charge is transferred from the imaging section 1 to the storage section 2) is lowered.
On the other hand, when the horizontal pitch P in the storage section 2 is selected to be small, then the ratio between the width W and the length L in the frame transfer is increased. However, the ratio between the width W and the length L of the transfer channel during a so-called line transfer in which the signal charge is transferred from the imaging section 2 to the horizontal shift register section 3 is reduced (in an inverse proportion fashion) and hence the transfer efficiency is lowered. Further, when the density of pixels is increased, then the number of pixels in the horizontal direction is increased so that the frame transfer frequency in the storage section 2 and the horizontal transfer frequency in the horizontal shift register section 3 are increased, which requires greater electric power.